CARUSO, Giuseppe
CARUSO, Giuseppe
Energia, Ingegneria dell'Informazione e Modelli Matematici (attivo dal 01/01/2013 al 31/12/2018)
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Risultati 1 - 11 di 11 (tempo di esecuzione: 0.024 secondi).
A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates
2013-01-01 CARUSO, G
A Design Methodology for Low-Power MCML Ring Oscillators
2007-01-01 CARUSO G; MACCHIARELLA A
A Methodology for the Design of MOS Current-Mode Logic Circuits
2010-01-01 Caruso, G; Macchiarella, A
Analysis of compressor architectures in MOS current-mode logic
2010-01-01 Caruso, G; Di Sclafani, D
Design of MOS current mode logic gates - Computing the limits of voltage swing and bias current
2005-01-01 CARUSO, G
Energy-Delay Efficiency of MCML Gates
2012-01-01 Caruso, G
Low-Power Design of Delay Interpolating VCO
2008-01-01 CARUSO G; MACCHIARELLA A
Minimum Power-Delay Product Design of MCML Gates
2008-01-01 CARUSO G; MACCHIARELLA A
Optimum design of MOS current mode logic gates
2004-01-01 CARUSO G
Optimum Design of Two-Level MCML Gates
2008-01-01 CARUSO, G; MACCHIARELLA, A
Power-aware design of MCML logarithmic adders
2010-01-01 Caruso, G