A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates

This paper presents a novel delay model for MCML circuits valid in all the regions of operation of the MOS transistor, i.e., weak inversion (sub-threshold), moderate inversion (near-threshold) and strong inversion. The proposed delay model was employed to develop an automated methodology for the energy-efficient design of such circuits. The tradeoff that can be realized between energy and delay was investigated. Experiments were performed using different technologies to understand the impact of technology scaling on that tradeoff too. Major results of this study are as follows. In a circuit designed for minimum energy consumption, the minimum energy point occurs in the near-threshold region and a noticeable reduction in delay is possible by relaxing the energy constraint. Moreover, technology scaling positively affects this tradeoff.