Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
CARUSO, G. (2005). Design of MOS current mode logic gates - Computing the limits of voltage swing and bias current. In IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005; Kobe; Japan; 23 May 2005 through 26 May 2005 (pp.5637-5640) [10.1109/ISCAS.2005.1465916].
Design of MOS current mode logic gates - Computing the limits of voltage swing and bias current
CARUSO, Giuseppe
2005-01-01
Abstract
Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.
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