In this work, an attempt is made toward the development of a systematic design method for the performance- driven dimensioning of the various elements comprising the structure of modern transistor-based microwave injection- locked oscillators with transmission-type topologies (TILOs). The proposed approach is based on the use of appropriate diakoptics of the various circuit blocks into a matched environment, and their behavioral modeling in the fundamental- frequency dynamical complex envelope domain with the help of standard circuit and E.M. simulation CAD tools. This will permit, in the end, to obtain closed-form expressions for the main TILO performances in terms of the design parameters, thus permitting their optimization as a function of system-level specifications. The practical validity of the method developed was tested by designing and building a single transistor 10.75GHz core-TILO with a wide locking bandwidth (>4MHz) at the low nominal input power level targeted (-20dBm).
Calandra, E., Lupo, D. (2010). Approach to the Design of Transmission-Type Injection-Locked Microwave Oscillators through Behavioral Block Modeling. In Proceedings of SM2ACD.
Approach to the Design of Transmission-Type Injection-Locked Microwave Oscillators through Behavioral Block Modeling
CALANDRA, Enrico;Lupo, Daniele
2010-01-01
Abstract
In this work, an attempt is made toward the development of a systematic design method for the performance- driven dimensioning of the various elements comprising the structure of modern transistor-based microwave injection- locked oscillators with transmission-type topologies (TILOs). The proposed approach is based on the use of appropriate diakoptics of the various circuit blocks into a matched environment, and their behavioral modeling in the fundamental- frequency dynamical complex envelope domain with the help of standard circuit and E.M. simulation CAD tools. This will permit, in the end, to obtain closed-form expressions for the main TILO performances in terms of the design parameters, thus permitting their optimization as a function of system-level specifications. The practical validity of the method developed was tested by designing and building a single transistor 10.75GHz core-TILO with a wide locking bandwidth (>4MHz) at the low nominal input power level targeted (-20dBm).File | Dimensione | Formato | |
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