Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM

This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGA-based Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The proposed simulator has been applied to control a PMSM. Specifically, two different minimum losses control techniques have been implemented as well as a space vector modulation of a three-phases voltage source inverter. The results given in this paper show the comparison of this two different algorithms and the effectiveness of the proposed HIL simulator.