Programming options for nanocrystal MOS memories

Nanocrystal memories represent a promising candidate for the scaling of FLASH memories. In these devices, the charge is not stored in a continuous floating gate but in a discontinuous layer composed by numerous discrete silicon quantum dots well separated one from the other.The nanocrystals of radius of few nanometers are realized by chemical vapor deposition (CVD) of silicon on the tunnel oxide of 2.8 nm of thickness. These islands have been coated with a control oxide of 7 nm formed by CVD and incorporated in Metal-Oxide-Semiconductor structure. The devices are programmed and erased by tunnelling using low voltages and fast times. In addition, the programming can be easily achieved also by channel hot electron injection (CHEI). Furthermore, such nanocrystal memory cells have been extensively characterized in order to study the possibility to achieve dual bit operation. In fact, during channel hot electron programming, the charge can be selectively injected only at the drain-side of the cell. This remains there localized due to the presence of the SiO2 between the grains which limits the lateral charge flow. The asymmetric charge distribution represents the key concept to the multi-bit storage. In this work, we show experimental evidence of such asymmetry. © 2003 Elsevier B.V. All rights reserved.