The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.

CALANDRA, E., DI MAIO, B., LUPO, D. (2007). On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers. In MWSCAS 2007 Conference Proceedings (pp.746-749). IEEE [10.1109/MWSCAS.2007.4488686].

On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers

CALANDRA, Enrico;DI MAIO, Bruno;Lupo, Daniele
2007-01-01

Abstract

The problem of evaluating the limit performances of cascaded single-ended multi-stage transistor amplifiers is addressed. In particular, a theoretically rigorous approach is proposed for the determination of a family of optimal design curves (ODC's) which express the best (maximum optimal) noise-gain tradeoff that can be achieved - at each operating frequency - when a simultaneous constraint on amplifier input VSWR is accounted for.
Settore ING-INF/01 - Elettronica
Midwest Symposium on Circuits and Systems
Montreal - Canada
5-8 Agosto 2007
50
2007
4
CALANDRA, E., DI MAIO, B., LUPO, D. (2007). On the Theoretical Limits of Noise-Gain-Mismatch Tradeoff in the Design of Multi-Stage Cascaded Transistor Amplifiers. In MWSCAS 2007 Conference Proceedings (pp.746-749). IEEE [10.1109/MWSCAS.2007.4488686].
Proceedings (atti dei congressi)
CALANDRA, E; DI MAIO, B; LUPO, D
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10447/33122
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