A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
DI STEFANO, A., SCAGLIONE, A., GIACONIA, C. (2005). Efficient FPGA Implementation of an Adaptive Noise Canceller. In Proceedings - International Workshop on Computer Architecture for Machine Perception (pp.87-89) [10.1109/CAMP.2005.22].
Efficient FPGA Implementation of an Adaptive Noise Canceller
DI STEFANO, Antonio;GIACONIA, Giuseppe Costantino
2005-01-01
Abstract
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
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