Memory cell structure integrated on semiconductor

This invention relates to a memory cell Which comprises a capacitor having a ?rst electrode and a second electrode separated by a dielectric layer. Such dielectric layer com prises a layer of a semi-insulating material Which is fully enveloped by an insulating material and in Which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the ?rst or to the second electrode, depending on the electric ?eld betWeen the electrodes,therebyde?ningdifferentlogiclevels.